I2C serial bus consists of two serial lines which are Serial Data line (SDA) and Serial Clock line (SCL), which are responsible for data transmission and clock signal, respectively. The master/slave communication mode is adopted as its communication manner, in which a master device initiates communication (read/write request) and provides a bus clock signal. A slave device acknowledges to the request of the master device, for instance, judging various addresses, command bit, data, acknowledgement bit, etc. transmitted by the master device determined in time, and then controls a register to adjust the mode of its own through software configuration according to a different mode, so as to communicate with the master device.
In a traditional I2C design, the next byte of data is triggered to be transmitted according to the empty and full of a data register. Therefore, when the slave device is in a transmission state, the data register becomes empty after the last byte of data has been transmitted, in which a transmission request flag signal will still be triggered and the data will still be filled into the data register, as indicated by the dashed box in FIG. 1. The master device provides a clock signal for the slave device, which is 9 cycles during which one byte of data is transmitted each time. An interrupt will be triggered when the data register is empty, and data should be filled in time, when the slave device is in transmission mode. Otherwise, an underflow may occur. Additionally, another interrupt will be triggered when the data register is full, and the data should be read in time, when the slave device is in a reception mode. Otherwise, an overflow may occur. The master device has obtained all bytes of data after the last byte of data has been transmitted when the slave device is in the transmission mode. However, since the slave device is in the transmission mode, an interrupt will still be triggered again to indicate the slave device to write data to be transmitted to the data register when the data register is empty, while the slave device should not write new data to the data register anymore at this time.
In order to restrain the slave device from continuing transferring data to the master device after all the data requested by the master device has been transmitted by the slave device, it is necessary to stop trigging data transmission after the last byte of data has been transmitted, and the following manners may be used:
In the first manner, the interrupt for the transmission data register empty (TxE) may be disabled to overcome the drawback (i.e., keeps waiting for filling new data) which occurs after the last byte of data has been transmitted when the slave device is in the transmission mode. However, to disable the interrupt for the transmission data register empty requires hardware to be independently supported in this manner. In addition, a new problem, which is how to enable the interrupt for the transmission data register empty, occurs even if the interrupt for the transmission data register empty is disabled. For instance, logic judgments shall be added into the interrupt for the reception data register full (RxF) by the slave device to enable the interrupt for the transmission data register empty to make the slave device the transmission mode again, if a command to request the slave device to transmit data again is received from the master device when the slave device has transmitted all data and has been switched to the reception mode.
In the second manner, the operation mode of the slave device is switched to the reception mode, and a reception data register is null-read again to make the interrupt for the reception data register full not trigger, such that the interrupt is disabled to stop the slave device transmitting data to the master device. However, the process is complex, and the operations during the process are not easy to comprehend. In addition, there will be plenty of status bits that have to be judged, and the operation mode of the slave device will be repeatedly switched to be in the transmission mode or the reception mode, when data transmission frequently happens between the slave device and the master device.
In the third manner, the empty transmission data register is filled by writing dummy data, thereby preventing the slave device from hanging in the interrupt for the transmission data register empty. However, writing the dummy data may cause a data error when the slave device transmits data again, such that the data transmission shall be affected.